1. Field of the Invention
The present invention relates to a substrate, an electronic component, and a manufacturing method of these.
2. Description of the Related Art
There has conventionally been known an electronic component manufactured by forming a conductive portion in a substrate (single-layer board) so as to penetrate a base of the substrate, which comprises the base made of an insulating material and conductive layers formed on the upper and lower surfaces of the base, and by stacking such single-layer boards, in which the conductive portion is formed, and connecting the single-layer plates (interlayer connection). The conductive portion in the single-layer boards used in this type of electronic component is formed by, for example, a method described below. FIG. 16 and FIG. 17 are diagrams for explaining the steps of forming the conductive portion of the single-layer boards.
First, a base 1 made of an insulating material is prepared, which has a predetermined thickness, on whose upper surface a conductive film 2 is formed, and on whose lower surface a lower conductive layer 3 is formed. A dry film 6 to serve as a resist is adhered to the base 1 so as to cover the conductive film 2, and then subjected to exposure and development, thereby to form a hole 7 corresponding to the diameter of a later-described conductive portion, as shown in FIG. 16A. Next, the conductive film 2 exposed at the bottom of the hole 7 is etched to remove the conductive film 2 exposed in the hole 7, and to expose the base 1 as shown in FIG. 16B. After the base 1 is exposed at the bottom of the hole 7, the dry film 6 is separated and an opening portion 8 corresponding to the diameter of the hole 7 is formed by laser irradiation to expose the lower conductive layer 3, as shown in FIG. 16C. Then, after the exposed surface of the lower conductive layer 3 and the formed opening portion 8 are subjected to desmear and these surfaces are cleaned, nonelectrolytic plating, which uniformly becomes chemical plating, is applied to the upper layer side of the substrate 1 and to the opening portion 8 to form a nonelectrolytic plated layer 9, as shown in FIG. 16D.
After the nonelectrolytic plated layer 9 is formed, electrolytic plating is applied with the nonelectrolytic plated layer 9 used as a power feeding film (electrode), to deposit a metal 10 inside the opening portion 8 and on the conductive film 2 as shown in FIG. 17A. Then, after the inside of the opening portion 8 is filled with the metal 10 by electrolytic plating as shown in FIG. 17B, the conductive film 2 and the lower conductive layer 3 are patterned by a subtractive method to form an upper wiring pattern 4 and a lower wiring pattern 5, and a conductive portion 11 is formed in the opening portion 8, as shown in FIG. 17C.
Further, as a method for forming a conductive portion of a single-layer board, also known are, for example, a method of using a nonelectrolytic plated layer at the bottom of a through hole to improve the air tightness between the base and the conductive portion, with reference to Unexamined Japanese Patent Application KOKAI Publication No. H5-335713, and a method of applying other treatments instead of nonelectrolytic plating, with reference to Unexamined Japanese Patent Application KOKAI Publication No. 2003-110211.
However, when electrolytic plating is applied after the nonelectrolytic plated layer 9 is formed to fill the opening portion with the metal 10, the plated layers are formed thick on the entire surface of one side of the base 1 because the nonelectrolytic plated layer 9 and the metal 10 are formed on the conductive film 2. This decreases the pattern etching performance, and the cross section of the wiring pattern becomes trapezoidal as shown in FIG. 17C when the wiring pattern is formed by etching, causing problems that the accuracy of the dimensions is reduced and a wiring pattern with narrow widths cannot be formed.
Furthermore, when the nonelectrolytic plated layer 9 is formed and electroplating is applied with the nonelectrolytic plated layer 9 used as an electrode, fresh plating solution is applied more to the surface of the nonelectrolytic plated layer 9 than to the inside of the opening portion. This promotes the growth of the electroplated layer on the surface, blocking the opening portion 8 with the electroplated layer before the metal 10 is filled in the opening portion 8, and possibly producing an empty space (so-called void) inside the conductive portion 11.
The same problem might occur even in a case where another pretreatment is applied, without using nonelectrolytic plating.
In a case where nonelectrolytic plating as the pretreatment of electroplating or another pretreatment similar to nonelectrolytic plating (hereinafter these will be referred to as nonelectrolytic plating, etc.) is used, a metal catalyst is used in order to adhere plate to also other portions (insulating portions) than the conductive portion. However, if the metal catalyst remains on the surface of the wiring layer, troubles such as a decrease of the insulating resistance, a short circuit in the wiring pattern, etc. might be caused. Particularly, recent electronic components adopt narrower pitches, and the possibilities of such troubles are more and more increased.